Job Information
Intel Memory Design Engineer in Hillsboro, Oregon
Job Description
About Advanced Design:
The Advanced Design organization delivers critical technology and design collaterals to enable future product designs. Critical to our mission, AD develops the first chips for all new Intel technology nodes. Intel prides to ensure process and design enablement are robust for high-volume product manufacturing.
The Group:
You will be part of Intel's Advanced Design Organization (AD) within Design Enablement (DE), focused on memory design and pathfinding where you will develop advanced memory technology and circuits to enable best-in-class memory collateral/IP and product design across all generations of Intel process technology.
The Role:
As a member of our team, your responsibilities will include (but not limited to):
Custom digital memory circuit design. Memory pathfinding.
Power performance area (PPA) optimization through design technology co-optimization (DTCO).
Product/design enablement. Bitcell and periphery layout design.
Process design kit enablement and support. Design Automation.
Memory array/IP design, memory circuit innovation, testchip design, execution, and validation.
Pre- and post-Si validation and debug to enable yield and parametric tracking and ramp.
#DesignEnablement
Qualifications
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualification:
Candidate must possess a MS degree with 3+ years of experience or PhD degree with 1+ years of experience in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline.
Experience above in the following:
Custom circuit design, simulation, layout design, and verification.
EDA tools used for digital and mixed-signal circuit design.
Knowledge of memory bitcell and memory circuit design.
Preferred Qualifications:
Experience above in the following:
CMOS process technology and device physics.
Design, characterization, optimization and verification of memory circuits such as SRAM, Register Files, ROM, etc.
Physical design / layout optimization on custom circuits
Design rule and construction rule definition.
Design trade-off of power, performance, and area (PPA).
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.