Job Information
Google Hardware Engineer, FPGA Design, Quantum AI in Goleta, California
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, a related field, or equivalent practical experience.
Experience in FPGA design and development.
Experience with RTL design using Verilog or System Verilog.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
Experience with DACs, ADCs and communication protocols such as Ethernet, PCIe.
Basic software knowledge in C/C++, Python.
Understanding of FPGA architectures, synthesis, timing analysis, clock domain crossing, and development tools (e.g., Vivado, Quartus).
Demonstrated ability to solve complex design challenges and debug FPGA systems.
The Quantum team's mission is to make state-of-the-art quantum computing tools available to the world to enable humankind to solve problems that would otherwise be impossible. The Quantum electronics team is carrying out a broad range of R&D aimed at implementing the best quantum computers in the world, with a long-term goal of realizing a fault-tolerant quantum computer.
In this position, you will contribute to the development of robust and scalable FPGA-based architectures that are essential for realizing the full potential of quantum computing. Your solid grasp of digital design and verification methodologies will be used to ensure the reliability and correctness of FPGA designs. You will ensure functionality of deployed systems. As part of the Quantum Computing team, you will have the opportunity to contribute to transformative projects at the forefront of quantum computing research, pushing the boundaries of computation and unlocking new possibilities in science and technology.
The US base salary range for this full-time position is $122,000-$178,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google (https://careers.google.com/benefits/) .
Develop efficient microarchitecture, RTL code using Verilog/System Verilog to realize complex digital logic designs on FPGAs. Synthesize and optimize FPGA designs for performance and resource utilization.
Create test benches and plans to verify FPGA designs, ensuring functionality and correctness through simulations and testing.
Identify and resolve issues in RTL and post-synthesis stages using debugging tools and methodologies.
Maintain design documentation and communicate progress and findings effectively in meetings and reviews.
Stay updated on FPGA technology and collaborate closely with cross-functional teams to achieve project objectives.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also https://careers.google.com/eeo/ and https://careers.google.com/jobs/dist/legal/OFCCPEEOPost.pdf If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form: https://goo.gl/forms/aBt6Pu71i1kzpLHe2.