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Apple Senior SerDes System Validation Engineer in Cupertino, California

Senior SerDes System Validation Engineer

Cupertino,California,United States

Hardware

Lead system validation of mixed-signal SerDes IP In this highly visible role, you will actively work within Analog-Mixed/Signal design team and participate in validation and debug of embedded circuits; collaborating with many disciplines to enable the world’s premiere products. You will closely work with a talented group of Analog-Mixed/Signal designers working diligently to deliver hard IPs to Apple’s products while exceeding the highest expectations of quality, innovation and efficiency. At Apple, we work every single day to craft products that enrich people’s lives. And in doing so face great challenges as SOC/PHY design complexity. If you have strong fundamentals and a track record of tackling technical challenges. If you are inspired by your curiosity and eagerness to learn new skills and to maximize the value and impact of your work. If you like to be tuned to the bigger-picture while diving deeply into the details to innovate and solve problems. If you love working with people and diverse teams to accomplish great things. If you like fire-fighting when challenges occur while keeping a phenomenal team spirit. If you care about society and have demonstrated leadership skills through commitment to great causes. We have an opportunity for a forward-thinking and especially hardworking system validation engineer with strong background in high speed serial links. As a member of our dynamic team, you will have the rare and rewarding opportunity to work on upcoming products that will surprise and delight millions of Apple’s customers everyday. And all of this while enjoying a great culture where you own your career.

Description

The ideal candidate should have experience in high-speed serial links with expertise in the following: • Very knowledgeable about and experienced with common high-speed SerDes protocols (e.g., PCIe, USB, UCIe, OIF, etc.) • Very knowledgeable in system bring-up of high-speed serial links, lab testing, and defining equipment needs • Very knowledgeable in scripting (e.g. python, C, Matlab) for automation of validation efforts. Experience with system level S/W setup is a plus • Experience in mixed-signal circuit pre-silicon verification and ability to closely work with circuit design team • Knowledge of DFT to aid in the system validation • Experience in leading mixed-signal SerDes system validation • Experience with silicon bring-up, debug and production ramp • Knowledge of SerDes design and architecture including CDR and equalization • Knowledge of with Tx/Rx equalization techniques and adaptation • Knowledge of link jitter budget for high-speed serial links and key block level requirements • Knowledge of ADC based links and equalization techniques • Familiarity with PCB design and specifications • Strong communication, teamwork and problem solving skills • Proven track record of delivering under difficult debug and validation scenarios Experience in the following areas is desirable: • Able to think outside of the box and come up with creative solutions for system validation • Knowledge of system level considerations e.g. ESD requirements

Minimum Qualifications

  • MSEE with 10+ years relevant experience or PhD with 7+ years relevant experience.

Key Qualifications

Preferred Qualifications

  • • Ownership of SerDes system bring-up, validation and debug. This will involve a SerDes bring up in system environment, verifying basic operations, analyzing robustness and margins in system.

  • • Work with design teams to understand the architecture and define DFT needs to help enhance testability and first time silicon success.

  • • Be involved in mixed-signal verification tasks to better understand the SerDes operation and interaction with higher level control logic.

Education & Experience

Additional Requirements

Pay & Benefits

  • At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $207,800 and $312,200, and your base pay will depend on your skills, qualifications, experience, and location.Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.Learn more (https://www.apple.com/careers/us/benefits.html) about Apple Benefits.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant. (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf)

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Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant (Opens in a new window) .

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