Job Information
Apple ASIC Design Engineer in Cupertino, California
ASIC Design Engineer
Cupertino,California,United States
Hardware
Are you an engineer looking to take on larger responsibilities while keeping a keen eye on the details? Do you enjoy working cross-functionally to solve multi-disciplinary problems end to end? Join our team of highly motivated, high caliber, detail-oriented problem solvers. As an ASIC Design Engineer, your primary responsibilities will include chip architecture definition, block/function definition, specification, RTL design and simulation of digital functions on complex ASICs for next generation Apple products.
Description
• Work with system and architecture teams to define chip requirements • Define top level chip architecture and develop detailed uArch specifications for digital block functions • Implement the functions in Verilog RTL to specification • Utilize state of the art low power design techniques to achieve aggressive power targets • Support the DV team in verification closure for achieving first pass silicon • Perform all design integration activities like Lint, CDC, RDC, Synthesis & ECO • Work with Physical Design Team on resolving STA, physical, power and logical issues • Collaborate with internal and cross-functional Firmware, Si validation and System stakeholders
Minimum Qualifications
BS + 10 years of relevant experience
Proven track-record in ASIC design including arch definition, uarch development and Verilog RTL design experience
Knowledge of best practices with respect to implementation of digital logic
Experience in Low Power design methodology
Experience with multiple clock domains and asynchronous interfaces
Power user of industry standard design tools and flows for logic synthesis, timing constraints, timing closure, STA, equivalence checking and other front-end tools
Flow automation scripts using Perl/Python, Tcl, or shell scripts
Key Qualifications
Preferred Qualifications
MS + 10 years of relevant experience
Experience in Processor subsystems, High speed serial interfaces or DSP is a plus
Experience with on-chip bus protocols such as AMBA AXI, AHB, APB is a plus
Experience in hands-on lab evaluation and silicon bringup
Understanding of Design Verification methodology
Understanding of ASIC test methodology such as scan insertion, memory BIST and test pattern generation
Education & Experience
Additional Requirements
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,800 and $312,200, and your base pay will depend on your skills, qualifications, experience, and location.Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.Learn more (https://www.apple.com/careers/us/benefits.html) about Apple Benefits.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant. (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf)
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